1. Field of the Invention
The present disclosure generally relates to the fabrication of integrated circuits, and, more particularly, to various methods of forming gate structures for FinFET devices and the resulting semiconductor devices.
2. Description of the Related Art
In modern integrated circuits, such as microprocessors, storage devices and the like, a very large number of circuit elements, especially transistors, are provided and operated on a restricted chip area. Immense progress has been made over recent decades with respect to increased performance and reduced feature sizes of circuit elements, such as transistors. However, the ongoing demand for enhanced functionality of electronic devices forces semiconductor manufacturers to steadily reduce the dimensions of the circuit elements and to increase the operating speed of the circuit elements. The continuing scaling of feature sizes, however, involves great efforts in redesigning process techniques and developing new process strategies and tools so as to comply with new design rules. Generally, in complex circuitry including complex logic portions, MOS technology is presently a preferred manufacturing technique in view of device performance and/or power consumption and/or cost efficiency. In integrated circuits including logic portions fabricated by MOS technology, field effect transistors (FETs) are provided that are typically operated in a switched mode, that is, these devices exhibit a highly conductive state (on-state) and a high impedance state (off-state). The state of the field effect transistor is controlled by a gate electrode, which controls, upon application of an appropriate control voltage, the conductivity of a channel region formed between a drain region and a source region.
To improve the operating speed of FETs, and to increase the density of FETs on an integrated circuit device, device designers have greatly reduced the physical size of FETs over the years. More specifically, the channel length of FETs has been significantly decreased, which has resulted in improving the switching speed of FETs. However, decreasing the channel length of a FET also decreases the distance between the source region and the drain region. In some cases, this decrease in the separation between the source and the drain makes it difficult to efficiently inhibit the electrical potential of the source region and the channel from being adversely affected by the electrical potential of the drain. This is sometimes referred to as a so-called short channel effect, wherein the characteristic of the FET as an active switch is degraded.
In contrast to a FET, which has a planar structure, a so-called FinFET device has a three-dimensional (3D) structure. FIG. 1A is a perspective view of an illustrative prior art FinFET semiconductor device “A” that is formed above a semiconductor substrate B that will be referenced so as to explain, at a very high level, some basic features of a FinFET device. In this example, the FinFET device A includes three illustrative fins C, a gate structure D, sidewall spacers E and a gate cap layer F. The gate structure D is typically comprised of a layer of insulating material (not separately shown), e.g., a layer of high-k insulating material or silicon dioxide, and one or more conductive material layers (e.g., metal and/or polysilicon) that serve as the gate electrode for the device A. The fins C have a three-dimensional configuration: a height H, a width W and an axial length L. The axial length L corresponds to the direction of current travel in the device A when it is operational. The portions of the fins C covered by the gate structure D are the channel regions of the FinFET device A. In a conventional process flow, the portions of the fins C that are positioned outside of the spacers E, i.e., in the source/drain regions of the device A, may be increased in size or even merged together (a situation not shown in FIG. 1A) by performing one or more epitaxial growth processes. The process of increasing the size of or merging the fins C in the source/drain regions of the device A is performed to reduce the resistance of source/drain regions and/or make it easier to establish electrical contact to the source/drain regions. Even if an epi “merger” process is not performed, an epi growth process will typically be performed on the fins C to increase their physical size.
In the FinFET device A, the gate structure D may enclose both sides and the upper surface of all or a portion of the fins C to form a tri-gate structure so as to use a channel having a three-dimensional structure instead of a planar structure. In some cases, an insulating cap layer (not shown), e.g., silicon nitride, is positioned at the top of the fins C and the FinFET device only has a dual-gate structure (sidewalls only). Unlike a planar FET, in a FinFET device, a channel is formed perpendicular to a surface of the semiconducting substrate so as to reduce the physical size of the semiconductor device. Also, in a FinFET, the junction capacitance at the drain region of the device is greatly reduced, which tends to significantly reduce short channel effects. When an appropriate voltage is applied to the gate electrode of a FinFET device, the surfaces (and the inner portion near the surface) of the fins C, i.e., the vertically oriented sidewalls and the top upper surface of the fin, form a surface inversion layer or a volume inversion layer that contributes to current conduction. In a FinFET device, the “channel-width” is estimated to be about two times (2×) the vertical fin-height plus the width of the top surface of the fin, i.e., the fin width. Multiple fins can be formed in the same foot-print as that of a planar transistor device. Accordingly, for a given plot space (or foot-print), FinFETs tend to be able to generate significantly higher drive current density than planar transistor devices. Additionally, the leakage current of FinFET devices after the device is turned “OFF” is significantly reduced as compared to the leakage current of planar FETs, due to the superior gate electrostatic control of the “fin” channel on FinFET devices. In short, the 3D structure of a FinFET device is a superior MOSFET structure as compared to that of a planar FET, especially in the 20 nm CMOS technology node and beyond. The gate structures D for such FinFET devices may be manufactured using so-called “gate-first” or “replacement gate” (gate-last) manufacturing techniques.
Over recent years, due to the reduced dimensions of the transistor devices, the operating speed of the circuit components has been increased with every new device generation, and the “packing density,” i.e., the number of transistor devices per unit area, in such products has also increased during that time. As a result of such increased packing densities, the physical space between adjacent devices has become very small, which can lead to some problems in manufacturing. FIGS. 1B-1E are plan views that depict the manufacture of eight separate FinFET devices above four separated active regions so as to explain one current problem encountered when attempting to manufacture FinFET devices in applications requiring very high packing densities.
FIG. 1B is a plan view of an illustrative prior art integrated circuit product 10 at an advanced stage of fabrication. In general, the product 10 is comprised of eight illustrative FinFET devices 11A-11H, wherein two of each of the FinFET devices are above each of four spaced-apart active regions 12A-12D that are defined in a semiconductor substrate by regions 18 of an isolation material, such as trenches filled with silicon dioxide. In the depicted example, the FinFET devices 11A-11H share a common source or drain region, see, e.g., the FinFET devices 11A, 11B wherein they each have separate drain regions (DR) but a common source region (SR). In this particular example, each of the FinFET devices 11A-11H is comprised of five illustrative fins 14 and an illustrative gate structure 16. A layer of insulating material 13 would have been formed between the fins 14 on active regions 12A-12D so as to locally isolate the fins 14 from one another. At this point in the process flow, the gate structures 16 would include sidewall spacers and a cap layer (each of which are not separately shown) so as to encapsulate and protect the gate electrode and gate insulation materials. In this particular example, the FinFET devices 11A-11D formed above the active regions 12A-12B share common gate electrodes, while the FinFET devices 11E-11H formed above the active regions 12C-12D are depicted as having separate gate electrode structures 16. The gate electrodes for the FinFET devices are typically formed by patterning one or more layers of material, i.e., the gate stack materials, to define long parallel line-type structures, i.e., gate electrode structures that extend across multiple active regions and multiple isolation regions. These long, line-type gate electrode structures are initially patterned so as to have the desired critical dimension (i.e., the dimension of gate electrode corresponding to the gate length of the finished device). That is, the sides 16Y of the line-type gate electrode structures 16 are patterned first. At some point later in the process flow, these long, line-type gate electrode structures are subsequently “cut” by performing an etching process to define the final gate electrodes. That is, the ends 16X of the line-type gate electrode structures 16 are patterned last so as to thereby define the final gate electrodes. The region 15 in FIG. 1B depicts the cuts made in the gate structures 16 formed above the active regions 12C-12D.
FIG. 1C depicts the product 100 after a selective epitaxial deposition process, i.e., a fin “merger” process, has been performed to form an epi semiconductor material 20 on the exposed portions of the fins 14. For reference purposes, the fins 14 formed above the active region 12A are depicted in dashed lines in FIG. 1C.
FIG. 1D depicts the product 100 after conductive contact structures 22 have been formed so as to establish electrical connection to the merged source/drain regions of the FinFET devices 11A-11H. The contact structures 22 would have been formed in contact openings formed in a previously formed layer of insulating material (not shown) that was formed above the source/drain regions. The contact structures 22 may be formed from a variety of materials, e.g., tungsten. In some cases, the contact structures 22 are referred to as “trench-silicide” structures due to the fact that they may be formed in trench-type openings and a metal silicide is formed where the contact 22 engages the epi semiconductor material 20.
FIG. 1E is an enlarged view of a portion of the product 100 shown in FIG. 1D. In general, the ends 16X of the gate structures 16 must be designed such that they extend a distance 16D beyond the edge of the active regions so as to prevent undesirable “bridging” of the epi material 20, as reflected by the dashed arrow 30. To the extent such bridging occurs, then device failure may occur due to the presence of a short between the source/drain regions of the FinFET device. In one example, using current day technology, the distance 16D (spacing between the end of electrode 16 and the sidewall of fin 14) may be on the order of about 30-50 nm, while the end-to-end spacing 16R between electrodes 16 may be on the order of about 30-50 nm. One solution to remedy the potential for bridging of the epi material formed on the fins 14 would be to simply make the distance 16D large enough so that there is little, if any, potential form the undesirable bridging of the epi material. However, such a “solution” would lead to reduced packing densities, which is counter to the ongoing trend in the industry now and for the foreseeable future.
The present disclosure is directed to various methods of forming gate structures for FinFET devices and the resulting semiconductor devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.